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 CAT431L
Low-Voltage Adjustable Precision Voltage Reference
- 0.5% Tolerance FEATURES
s Low startup overshoot s Wide current operation: 40A to 100mA s Low temperature coefficient reference: +12mV s Low dynamic impedance: 0.3 at 1kHz s Compact 3-lead SOT23 package option s Industrial temperature range: -40C to 85C s Adjustable output voltage: VREF to 6V
- SOT23 and TO92 Packages
- Low Startup Overshoot
max deviation over temperature
s Accurate 1.24V reference voltage: +0.5%
(+6mV) at 25C
APPLICATIONS
s SMPS control loop s Shunt regulator s Low temperature coefficient voltage reference s Current limiting s Over/Under voltage monitor s 3V Off-line switching regulators
DESCRIPTION
The CAT431L is a low-voltage three-terminal adjustable shunt voltage reference with guaranteed thermal stability over the industrial temperature range. The CAT431L has a lower 1.24V reference and wider operating current range than the widely used TL431 and TL431A shunt-regulator references. Compared to the TLV431/A, the CAT431L 1.24V reference is two times more accurate. Minimal overshoot at startup and wide AC bandwidth make the CAT431L easy to apply in a wide set of applications. When used with an opto-coupler, the CAT431L is an ideal voltage reference in isolated feedback circuits for 3V to 3.3V switch-mode power supplies.
FUNCTIONAL DIAGRAM
CATHODE CATHODE REF
+ -
REF 1.24 VREF ANODE ANODE
(c) 2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 4006, Rev. J
CAT431L
PIN CONFIGURATION
SOT-23 TOP VIEW 2 CATH ANODE 3 1 REF NC 1 NC 2 CATH 3 4 REF SOT-23-5 TOP VIEW 5 ANODE
TO-92 TOP VIEW CATH ANODE REF
PIN DESCRIPTIONS
Pin Name CATH REF ANODE Function Output and supply terminal, must be greater than 1.24V for normal operation Input, nominally 1.24V in normal operation Ground and Substrate
ORDERING INFORMATION
Part Number CAT431LEUR-TE7 CAT431LEUK-TE7 CAT431LEZR-TEAP
TE7 = 7" Reel, 3,000 parts per reel TEAP = Ammopack, 3,000 parts per reel
Package 3-Pin, SOT-23 5-Pin, SOT-23 3-Pin, TO-92
Ambient Temperature Range -40 C to 85 C -40 C to 85 C -40 C to 85 C
Doc. No. 4006, Rev. J
2
CAT431L
ABSOLUTE MAXIMUM RATINGS
Cathode Voltage .................................................. 18V REF Current ........................................................ 3mA Cathode, Anode Currents ............................... 150mA Operating Junction Temperature ..................... 150C Lead Soldering Temperature (10 sec) ............. 260C Storage Temperature Range ........... -65C to +150C
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolongued time periods may affect device reliability. All voltages are with respect to ground.
ELECTRICAL CHARACTERISTICS
Electrical characteristics are guaranteed over the full operating temperature range of -40C to +85C with a junction temperature from -40C to +105C unless otherwise specified. Ambient temperature must be de-rated based upon power dissipation and package thermal characteristics.1 Symbol VREF VREF VREF VCATH IREF IREF ICATH(min) ICATH(OFF) rCATH
1.
Parameter Reference Voltage
Conditions VREF=VCATH ICATH=10mA 25 C TEMP
Min 1.234 1.228
Typ 1.240 1.240 4
Max 1.246 1.252 12 1 0.4 0.2 40 100
Units V V mV mV/V A A A nA
VREF Temperature deviation Ratio of VREF Change to VCATH Change (Line Reg; 1/gain) Reference input current IREF Temperature Deviation Minimum Cathode Current Off-State Cathode Current Dynamic Output Impedance VREF=0V; VCATH=16V ICATH=0.1 to 100mA f=1.0kHz ICATH=10mA VCATH=VREF to 6V ICATH=10mA
0.3 0.2 0.04 18
0.3
0.4
Thermal Characteristics (JA) 3-lead, SOT-23: 336C/W 5-lead, SOT-23: 255 3-pin, TO-92: 155
Recommended Operating Conditions
Parameter Cathode Voltage Cathode Current Operating Ambient Temperature
Min VREF 0.1 -40
Max 6 15 85
Units V mA
C
3
Doc. No. 4006, Rev. J
CAT431L
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage vs. Junction Temperature
1.246 1.244 250
Reference Input Current vs. Junction Temperature
Reference Input Current (nA)
240 230 220 210 200 190 180 170 160 150 -50 -25 0 25 50 75 100 125 150
Reference Voltage (V)
1.242 1.240 1.238 1.236 1.234 1.232 -50
-25
0
25
50
75
100 125 150
Junction Temperature (C)
Junction Temperature (C)
Cathode Current vs. Cathode Voltage
150 100 50 20 0 10 -50 -100 -1 -0.5 0 0.5 1 1.5 0 -10 -1 50 40 30
Cathode Current vs. Cathode Voltage
Cathode Current (mA)
0.5
1
1.5
Cathode Voltage (V)
Cathode Voltage (V)
Doc. No. 4006, Rev. J
4
CAT431L
TYPICAL PERFORMANCE CHARACTERISTICS Off-State Cathode Current vs. Junction Temperature
Off-State Cathode Current (nA)
80 0
Delta Reference Voltage Per Delta Cathode Voltage vs. Junction Temperature
Delta Reference Voltage per Delta Cathode Voltage (mV/V)
-0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -50 -25 0 25 50 75 100 125 150
70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150
Junction Temperature (C)
Junction Temperature (C)
Open Loop Voltage Gain vs. Frequency
100 80
100
Dynamic Impedance vs. Frequency
Open Loop Voltage Gain (dB)
60 40 20 0 -20 0.001
Dynamic Impedance (kohms)
10
1
0.1
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
5
Doc. No. 4006, Rev. J
CAT431L
Doc. No. 4006, Rev. J
6
CAT431L
TYPICAL APPLICATIONS
Shunt Voltage Regulator
Vo R1 0.1% VREF R2 0.1% R1 CAT431L Vo = 1 + R2 VREF
Flyback Converter with Optical Isolation
VI 120V
~
-
+
Gate Drive VCC Controller
GND
VFB Current Sense
CAT431L
7
(
(
Vo 3.3V
Doc. No. 4006, Rev. J
CAT431L
PACKAGE OUTLINES 3 LEAD SOT-23
b PIN #3
PIN #1
PIN #2
e
e1
D (4X)
8] .0 R0 3[ L) 0L .0 R0 (A
L1
A2
A
0.01[0.54]
E1
E
A1
c
L
NOTES: 1. ALL DIMENSIONS ARE IN INCHES & IN [ ] ARE IN MM. 2. PACKAGE OUTLINE DIMENSIONS INCLUSIVE OF METAL BURRS. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.076MM. [0.003"]. 4. ALL PACKAGE SURFACES TO BE MIRROR FINISH. 5. MOLDING AND FORMING WITH DIE FACING UP. 6. LEADFINISH PLATING: 0.00762MM [0.0003"] - 0.0254MM [0.001"]. PACKAGE OUTLINE EXCLUSIVE OF LEADFINISH PLATING. 7. THIS POD COMPLIES TO JEDEC TO-236AB ISSUE H.
Doc. No. 4006, Rev. J
8
CAT431L
5 LEAD SOT-23
1.900 0.950 PIN #5 PIN #4
PIN #1 PIN #3
0.350+0.150 -0.000
0.418+0.250
2.900+0.100
1.100+0.200
1.650+0.050 -0.150 BOTTOM PACKAGE
1.600 +0.050 -0.150 TOP PACKAGE
2.800+0.200
1.200+0.250
070
- 0 .1
30
0.100+0.050
0.575
R0.
0 02 0. 7+ 19 0. R
0.200
DATUM "A"
NOTES: 1. ALL DIMENSIONS ARE IN MM. 2. PACKAGE OUTLINE DIMENSIONS INCLUSIVE OF METAL BURR. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.076MM. 4. ALL PACKAGE SURFACE TO BE MIRROR FINISH. 5. MOLDING WITH DIE FACING UP, AND FORMING WITH DIE FACING DOWN. 6. FOOT LENGTH TO BE MEASURED AT THE INTERCEPT POINT OF EXTERNAL LEADS AND DATUM "A". 7. LEADFINISH PLATING: 0.00762MM - 0.0254MM. PACKAGE OUTLINE EXCLUSIVE OF LEADFINISH PLATING.
R0 .0 .0 -0 (4 30 .1 X)
0.152+0.008
0.400+0.150 -0.050
9
Doc. No. 4006, Rev. J
CAT431L
3 LEAD TO92
Branding surface
4.6 +/- 0.2
13.95 +/- 1.25
1.33 - 1.60
0.53 max. (TRIM)
0.405 +/- 0.045
0.458 min 0.505 max
3.55 +/- 0.15
R = 0.1 max 2.04 - 2.66
Round lead corners (R = 0.2)
0.38 (for lead tip only)
NOTE : 1.0 All dimensions are in mm. 2.0 Dimension tolerance of 0.05 mm unless otherwise specified. 3.0 Solder dipping finish @ 63/37 Sn/Pb. 4.0 Burrs in trim @ 0.13 mm max.
Doc. No. 4006, Rev. J
10
(PLANE AREA = 4.0)
4.6 +/- 0.1
1.27
2.54
4.3
CAT431L
REVISION HISTORY
Date 12/15/03 Rev. J Reason Updated typical performance characteristics legend for Delta Reference voltage
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM AE2 TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication #: Revison: Issue date: Type:
4006 J 12/15/03 Final
11
Doc. No. 4006, Rev. J


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